Rambus Delivers PCIe 6.0 Interface Subsystem for High-Performance Data Centers and AI SoCs
Press Release: Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced the availability of its PCI Express® (PCIe®) 6.0 Interface Subsystem comprised of PHY and controller IP. The Rambus PCIe Express 6.0 PHY also supports the latest version of the Compute Express Link (CXL) specification, version 3.0. “The rapid advancement of AI/ML and data-intensive workloads are driving the continued evolution of data center architectures requiring ever higher levels of performance,” said Scott Houghton, general manager of Interface IP at Rambus. “The Rambus PCIe 6.0 Interface Subsystem supports the performance requirements of next-generation data centers with best-in-class latency, power, area, and security.” The Rambus PCIe 6.0 Interface Subsystem delivers data rates of up to 64 Gigatransfers per second (GT/s) and has been fully optimized to meet the needs of advanced heterogenous computing architectures. Within the subsystem, the PCIe controller features an Integrity and Data Encryption (IDE) engine dedicated to protecting the PCIe links and the valuable data transferred over them. On the PHY side, full support for CXL 3.0 is available to enable chip-level solutions for cache-coherent memory sharing, expansion, and pooling. PCI Express layer
Designed to the latest PCI Express 6.0 (64 GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s), and PIPE 6.x (8, 16, 32, 64 and 128-bit) specifications Supports SerDes Architecture PIPE 10b/20b/40b/80b width Supports original PIPE 8b/16b/32b/64b/128b width Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification Supports multiple virtual channels (VCs) in FLIT and non-FLIT modes Supports Endpoint, Root-Port, Dual-mode, Switch port configurations Supports PCIe 6.0 to PCIe 1.0 speeds Supports Forward Error Correction (FEC) – Lightweight algorithm for low latency Supports L0p Low Power mode Up to 4-bit parity protection for data path Supports Clock Gating and Power Gating RAS features include LTSSM timers override, ACK/NAK/Replay/UpdateFC timers override, unscrambled PIPE interface access, error injection on Rx and Tx paths, recovery detailed status, and much more, allowing for safe and reliable deployment of IP in mission-critical SoCs
“PCIe is ubiquitous in the data center and CXL will become increasingly important as companies pursue ever-escalating speeds and bandwidths to support higher levels of performance in next-generation applications,” said Shane Rau, research vice president, Computing Semiconductors an IDC. “As a growing number of chip companies emerge to support new data center architectures, access to high-performance interface IP solutions will be key to enabling the ecosystem.” Key features of the Rambus PCIe 6.0 Interface Subsystem include:
Supports PCIe 6.0 specification including 64 GT/s data rate and PAM4 signaling Implements low-latency Forward Error Correction (FEC) for link robustness Supports fixed-sized FLITs that enable high-bandwidth efficiency Backward compatible with PCIe 5.0, 4.0, and 3.0/3.1
